Gigabit Ethernet Interface (via Marvell 88E1111) with Cyclone IVE FPGA

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I am using Altera DE2-115 Board (CyloneIVE device) and want to connect some other device running in Gbps via its Gigabit Ethernet Transceiver (Marvell 88E1111) interface.

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The comment "running in Gbps" is a bit vague. Are you saying you want to capture an data stream that happens to be operating at Gbps data rate? If so, the answer is probably "No you cannot".

The Marvell PHY is designed for Gigabit data streams. The SGMII interface expects data encoded per whatever GbE encoding uses. It cannot be used to capture an arbitrary Gbps data stream.

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Can I get some idea about how can I proceed for this project?

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Consider buying a Cyclone IV GX Starter kit and use the Gbps signals on its PCIe edge connector.

If you can describe what you are trying to do in more detail, members of this forum can provide ideas.

Cheers,

Dave

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The comment "running in Gbps" is a bit vague. Are you saying you want to capture an data stream that happens to be operating at Gbps data rate? If so, the answer is probably "No you cannot".

The Marvell PHY is designed for Gigabit data streams. The SGMII interface expects data encoded per whatever GbE encoding uses. It cannot be used to capture an arbitrary Gbps data stream.

Consider buying a Cyclone IV GX Starter kit and use the Gbps signals on its PCIe edge connector.

If you can describe what you are trying to do in more detail, members of this forum can provide ideas.

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Let me clarify little more:

At first, I want to interface Ethernet MAC with Cyclone IVE by means of Marvell PHY (MII/RGMII Interface) . The data stream is still not fixed but it will be close to Gigabit.

It seems that Tripple Speed Ethernet MAC could fulfill my task. I am planning to use following Megacore function:

http://www.altera.com/literature/ug/ug_ethernet.pdf

one more thing, do I need any license to use Megacore function (Tripple Speed Ethernet MAC) with QuartusII Web edition or its free like FIFO?

Is it worthy to proceed in this way or should I use some other alternative if any?

Regards

Sheikh

Yes the core should be good for the job. It does requires an extra license so it isn't free.

Are you using a development kit? If so you should already have an example design with the TSE Mac that you can look at.

If you are making your own board I would strongly suggest to consider alternatives to the Marvell PHY because Marvell is very annoying with the way they handle datasheets. They require you to sign a restrictive NDA before sending you any documentation.

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Let me clarify little more:

At first, I want to interface Ethernet MAC with Cyclone IVE by means of Marvell PHY (MII/RGMII Interface) . The data stream is still not fixed but it will be close to Gigabit.

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This interface "requirement" is still too vague - "close to Gigabit" is not a definitive statement.

If your protocol is uncertain, then you should really consider interfacing to the Gbps data stream *directly*. The Cyclone IV GX devices are inexpensive, and you will not have to deal with Marvell and its annoying NDAs.

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Is it worthy to proceed in this way or should I use some other alternative if any?

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Create a simulation of the data stream and capture it using a Cyclone IV GX transceiver channel.

If the Gbps data stream is ~1Gbps, then you can also consider using LVDS on a Stratix series device.

Cheers,

Dave

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Are you using a development kit? If so you should already have an example design with the TSE Mac that you can look at.

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Yes, I am using Development kit (DE2-115 having Cyclone IVE device) and it has the Marvell PHY (88E1111). I couldn't find an example design with the TSE Mac in the provided CD. Instead I found "10_100_1000 Mbps Tri-mode Ethernet MAC" which also uses Marvell PHY (88E1111) and written in verilog on Opencores.org but I don't know how to use it. can I get some idea how to proceed?

Yes sorry, I somewhat missed your first post where you said you were using the DE2-115.

It doesn't look like the CD contents are available on Altera's web site (contrary to the non-education development kits) so I can't have a look. But on the board's page (http://www.altera.com/education/univ/materials/boards/de2-115/unv-de2-115-board.html), there seems to be a tutorial in PDF about setting up Altera's TSE: ftp://ftp.altera.com/up/pub/altera_material/12.1/tutorials/de2-115/using_triple_speed_ethernet.pdf (and design files here: ftp://ftp.altera.com/up/pub/altera_material/12.1/tutorials/de2-115/using_triple_speed_ethernet_on_de2_115_design_files.zip ). It's strange they didn't think about putting those on the kit's CD.

Hi Daixiwen,

I am trying to implement the tutorial you provided for TSE_MAC and getting following error while generation using Qsys.

0 [main] sh 1248 c:\Altera\12.0sp2\quartus\bin\cygwin\bin\sh.exe: ***fatal error- WFSO timed out after longjmp.

The screen shot is in attchment for better clarification.https://www.alteraforum.com/forum/attachment.php?attachmentid=7614

What is the solution for this error?

Hi,

I am getting following error while using Altera Monitor Program to apply above tutorial:

usr\bin\bash nios2-app-generate-makefile: command not found

I looked on some post, they say NIOS IDE should be installed in the directory without space. I already have both nios IDE and Quartus installed in the directory without space. The project directory is also without space.

what could be problem then?