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Altera_Forum's avatar
Altera_Forum
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20 years ago

FPGA programming Problem

Hello

This is not a really Nios problem but an FPGA problem. I have the Nios II development Kit with the cyclone II. I want to write a very small and easy VHDL code example to test the Development tools. My VHLD code has a single process which is sensitive on the clock and if the input is 1 the output gets one to.

I connect the clock to the Pin_N2 the input to the Pin_Y11 (button) and the output to the Pin_W11 (led) after progamming this simple test on the board it wors very shortly and than rests again and loads the factory programmed programm out of the flash. Why does this happen. Should a process not be available for ever. Why does the bord resets?

I hope you can help me

thx flo

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    I don't know cyclone II kit, but altera dev kits have a configuration epld

    which is triggered by a special pin (pld_RECONFIGREQ_n) to reload

    the fpga. set this pin inactive in your design.

    also set unused pins = as inputs tristated in your design.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Thank you first

    But i'm not sure how to set a pin inactive Do i have to set this pin to '0' in my module? Or can i do this in some quartus settings?

    mfg flo
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    pld_RECONFIGREQ_n (active low) seems to have a pullup,

    so it should be sufficient to set "unused pins = as inputs tristated"

    in quartus assignement->settings->device->device%pin options

    ->unused pin.

    you can additional make an output pin pld_RECONFIGREQ_n and connect it to

    VCC in your top schematic.