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Altera_Forum's avatar
Altera_Forum
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20 years ago

FPGA programming Problem

Hello This is not a really Nios problem but an FPGA problem. I have the Nios II development Kit with the cyclone II. I want to write a very small and easy VHDL code example to test the Development...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

pld_RECONFIGREQ_n (active low) seems to have a pullup,

so it should be sufficient to set "unused pins = as inputs tristated"

in quartus assignement->settings->device->device%pin options

->unused pin.

you can additional make an output pin pld_RECONFIGREQ_n and connect it to

VCC in your top schematic.