Altera_Forum
Honored Contributor
20 years agoFlash Programmer Problems
Hi Everyone,
I have built a target board in SOPC builder in order to program the flash memory on my board. The target board contains an EPCS controller and CFI flash controller (the actual board does not actually have a CFI flash device, it only has an EPCS device. I'm following the advice given on Altera's Nios II errata webpage). The error I'm getting is the same as ppl in previous posts have got, ie, 'Unable to synchronize with target' after downloading the target board SOF onto the FPGA. I have a reset delay block in the design. I'm pretty sure this works because I've tried it on another Nios II system and it works fine in that I am able to download and execute code on the processor. The clock to the system to is 100 MHz. I have also replaced the firmware_ROM.hex file as suggested in the Altera website. I have no hardware image setting for the EPCS device as of now. Has anyone out there encountered a similar problem? Is there something I'm missing? Is there a way to debug this and figure out what's going wrong where? Thanks a lot.