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Altera_Forum's avatar
Altera_Forum
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15 years ago

FLASH command via NIOS IO.h

Hi,

I'd like to activate dynamic protection sectors ( DYB ) of a 16 bits CFI FLASH SG29GL256N, but I'm facing issues with the IOWR_16DIRECT command of the io.h :

when I look the FLASH signals with Signal Tap, writes to odd addresses are OK but writes to even ones don't activate flash signals.

The config is the following :

- Quartus 9.1, EDS 9.1

- NIOS access to FLASH via registered Tri State Bridge

- FLASH address bus [23:0] connected to NIOS FLASH address bus [24:1] in VHDL

- WR/RD OK when FLASH accessed by classic HAL functions

I don't use the IOWR command because of the 32 bit alignment (2 successives accesses are generated to the FLASH to produce a 32 bit data write).

So, following C code produces activation of relevant ad, data, ce_n and we_n signals :

IOWR_16DIRECT(CFI_FLASH_BASE,0x0555*2,0xAA);

But following produces nothing :

IOWR_16DIRECT(CFI_FLASH_BASE,0x0556*2,0xAA);

Does anybody have an idea ? Thanks in advance.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    IIRC the nios cpu will always do 32bit transfers to the Avalon slave, with the 4 byte enables being asserted appropriately.

    For a 16bit slave there will be a 'bus width adapter' that generates two cycles with the relevant byte enables copied across - even if it means a cycle has active byte enables!

    (Reads always assert all 4 byte enables.)

    It might be that you are only tracing the first of the two adjacent cycles!
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks for your answer.

    I understand the theory and I think it is applicable to the IOWR command (2 cycles seen at STP). This is why I use IOWR_16DIRECT (one cycle seen) to match with FLASH sequence.

    But when I execute the previous C code in debug mode, step by step, the Signal Tap (condition ce_n = 0 and we_n = 0) triggs on the first line but not on the second one (and I'm sure I don't miss a cycle ;-) ).

    In fact IORW is OK to access every address (odd or even) and nok because of the second cycle and for IOWR_16DIRECT, it's the invert ...
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I believe (I've not used them!) that IOWR_DIRRECT() generates an 'stwio' instruction and IOWR_16DIRECT() an 'sthio' instruction. Both these instructions will generate a 32bit Avalon master cycle, the first will have all 4 byte enables asserted, for the second only 2 byte enables are asserted.

    The 'bus width adapter' generates two cycles into the 16bit slave, for 'stwio' both will have the 2 bytes enables asserted, for the 'sthio' one of these cycles won't have any byte enables asserted.

    The Avalon slave cycle without any byte enables is probably invisible on the flash device itself.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    OK. So more generally, does anyone know how to successfully perform successives writes to a 16 bit FLASH with a NIOS ?

    The sequence shall be for example :

    Write number : 1 2 3

    AD : 555 2AA 555

    DATA : AA 55 E0