External SSRAM reading/writing problem

Hello everyone,

I want to connect nios core (cyclone ii) to external sram memory (cy7c1380d) but I'm experiencing a problem while reading/writing to/from the memory. For 2MB (data width 32 bits) memory I need 19 address bit, but the memory has 21 address bits. SOPC buider user guide says that Avalon-MM address[0] and address[1] should be left unconnected, but I don't know how to do that.

When I run an ssram test program, read and written data don't match.

unsigned int i;

alt_u32 *buffer = (alt_u32 *)SSRAM_BASE;

for(i=0; i<100; i++) {

buffer = (i+1000000);

}

for(i=0; i<100; i++) {

if(buffer != (i+1000000)) errors++;

}

So instead of this, I tried to do somthing like this:

buffer[0] = 0;

buffer[1] = 1;

...

buffer[50] = 50;

alt_printf("%x ", buffer[0]);

alt_printf("0x%x ", buffer[1]);

...

alt_printf("0x%x ", buffer[50]);

And here is what is printed:

0x30 0x31 0x32 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x23 0x24 0x25 0x26 0x27 0x28 0x29 etc.

So, apparently, the address 0, 16, 32 are overwritten with what I want to write to the address 48, address 3 with 35, etc... At first I thought that it could be a timing issue and I added a delay of -2ns (also tried -3ns, -5ns, 180deg) to the pll (25MHz) that is driving my external ssram, but it didn't solve the problem. There may be a problem with the address pins, and I'm not sure if SOPC builder left-alignes the address bits or I need to do that.

Thanks,

Nikola