Honored Contributor
Honored ContributorI don't think it would give any performance increase. Even if the Nios' data and instruction masters were trying to access the SSRAM simultaneously, I'm not sure the SOPC builder fabric would be able to blend those two together and take advantage on the increased speed. Also any clock crossing domain will add some latency, so you may end up with a slower system.
It could make sense if you had a fast DMA in your system though. For example a SSRAM and DMA running at 100Mhz, and the Nios kept at 50MHz (if you really don't want to run it at 100 MHz).
