External SSRAM reading/writing problem

If Nios is your only Avalon master, I don't know if using higher ssram frequency makes any sense.

Probably it'd rather worsen the timing, because of higher frequency signals and more

logic resources are required (a clock adapter needs to be inserted between nios and ssram).

You could have some advantage if your ssram requires multicycles or waitstates to perform some

operations; it this case a higher ssram frequency could avoid Nios stalls and improve performance.

This is useful with SDRAMs, where you have latencies due to precharge, refresh and row selection delays,

but with ssram you don't have this intrinsic delays. However, I know this kind of ssram

use some level of pipelining, so I believe it can lead to multicycle bus stalls if you frequently

use random access rather than burst or sequential accesses.

You must browse the datasheet for this information and define the optimal design

on the basis of the way your application uses the ssram device.

My advice is testing both configurations with some benchmark and find out which one gives you better results.