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Altera_Forum's avatar
Altera_Forum
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13 years ago

Ethernet autonegotiation

I am just wondering what kind of procedures are running during the link establishment in 100Base-T ethernet in case auto negotiation is disabled (i.e. forced mode) at both ends of the ethernet connection (i.e. switch and NIC)?

Thanks,

15 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Yes, parallel detection is used if one end has aneg enabled and the other doesn't. If both ends have aneg disabled, they both send idle, and the mac operates in whatever mode you specify (half/full). When either end sees idle, it establishes a link.

    Cheers,
  • Altera_Forum's avatar
    Altera_Forum
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    Actually the MAC itself always has to be told whether to do FDX or HDX, the driver has to extract that information from the PHY (or ignore the PHY and use a hard-coded value).

    The PHY configuration (and negotiation) control the speed. In some cases (eg some MAC using MII) the MAC doesn't need to know whether the PHY is doing 10M or 100M (I'm not sure about higher speeds).

    (I suspect we are agreeing violently!)
  • Altera_Forum's avatar
    Altera_Forum
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    Yes, I think that's what I said, the MAC has to be configured (one way or another) for duplex, via the driver polling the phy to get autoneg results, or manual control. I'm not a 10Mbps expert (most of my knowledge is 1G+), but NLPs (or link test pulses) are "idle" in 10Mbps, so yes, they are still sent in 10Mbps mode. In 100Mbps, FLPs are sent if aneg is enabled (until completion of the aneg process), otherwise it's MLT3 encoded idle.

    At higher speeds the mac interface is different, i.e. gmii or xgmii, etc.
  • Altera_Forum's avatar
    Altera_Forum
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    So do you know which specification explains MLT3 encoded idle message transmission procedures for 100Base-T case? I checked 802.3-2008 but could find much information. Should I look at previous versions?

  • Altera_Forum's avatar
    Altera_Forum
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    The actual PMD spec for 100Base-TX is covered by the FDDI TP-PMD standard, it's not in 802.3. It's a 3 level analog signal, nothing you can interface an FPGA directly to without some external components. If you're attaching to a PHY, all you need is an MII, and you can obtain link status (etc) from the PHY's MDIO interface.