Ethernet Arch - Nios2, TSE and MSGDMA IP-Cores - REF Design

Hi,

Greetings and welcome to Intel's forum.

Please give me some time to check on this issue and will get back to you with the update.

Thank you.

Regards,

Fathulnaim

Hi Amir,

Are you using this template?

https://www.intel.com/content/www/us/en/design-example/714912/intel-arria-10-fpga-nios-ii-processor-simple-socket-server-design-example.html

The closest reference design available I found for you based on your question above is this -

https://www.intel.com/content/www/us/en/design-example/714737/intel-cyclone-10-lp-fpga-hyperram-msgdma-reference-design.html

This reference design also come with tutorial.

Have a good day.

Regards,

Fathulnaim

Hi,

Do you have any updates to share about this issue?

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.