Forum Discussion
Altera_Forum
Honored Contributor
21 years agoEthernet and DMA
Hi everyone,
I'm working with a LwIP Stack (only using UDP) and make some timing measurements to find the nottlenecks of the stack. So I saw that the data transfer to the SMSC chip needs quiet some time. To reduce this time I added a DMA controller via SOPC builder. The problem is that when I start the DMA controller it will never end. The busy flag is set for ever. Does somebody use a DMA controller to get the data in the SMSC? Thx for your help revolt -------------------------------------------------------------------------------------------------------------------------------------------------------------------- SOPC Connections SDRAM -- DMA -- Tristate-Bridge -- SMSC int.SRAM / Code: int doDMAEthernet(volatile unsigned int* puiReadAddr,volatile unsigned int* puiWriteAddr,unsigned int uiLen) { while ((IORD_ALTERA_AVALON_DMA_STATUS(DMA_ETHERNET_BASE) & ALTERA_AVALON_DMA_STATUS_BUSY_MSK)); IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_ETHERNET_BASE,0); IOWR_ALTERA_AVALON_DMA_STATUS(DMA_ETHERNET_BASE, 0); IOWR_ALTERA_AVALON_DMA_LENGTH(DMA_ETHERNET_BASE, uiLen); IOWR_ALTERA_AVALON_DMA_RADDRESS(DMA_ETHERNET_BASE, puiReadAddr); IOWR_ALTERA_AVALON_DMA_WADDRESS(DMA_ETHERNET_BASE, puiWriteAddr); // Start DMA // WORD (32 BIT) transfer // LEEN = Ends transaction when length reg reaches zero, write to constant address // WCON = write to fix address IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_ETHERNET_BASE,ALTERA_AVALON_DMA_CONTROL_GO_MS K | ALTERA_AVALON_DMA_CONTROL_WORD_MSK| ALTERA_AVALON_DMA_CONTROL_WCON_MSK| ALTERA_AVALON_DMA_CONTROL_LEEN_MSK); while ((IORD_ALTERA_AVALON_DMA_STATUS(DMA_ETHERNET_BASE) & ALTERA_AVALON_DMA_STATUS_BUSY_MSK)); return 0; }8 Replies
- Altera_Forum
Honored Contributor
Probably in DMA settings (SOPC Builder) your set small value for length of transmitted words and "uiLen" much more.
- Altera_Forum
Honored Contributor
In the SOPC the max. DMA length is set to 512 Words. The problem occured when I try to transmit 10 Words.
- Altera_Forum
Honored Contributor
okay, I was my fault http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/rolleyes.gif
I wrote the number of word transfers into the length register instead of the length in bytes. In my case 10. Because of the word transfers the DMA counts 10, 6, 2, -2 . . . So the length will never reach the value zero which would stop the DMA. - Altera_Forum
Honored Contributor
hi Revolt,
Could you please post you performance measurements here? The LWIP stack is quite slow over here, so it would be nice to know if DMA can speed it up Thanks, Jmastron - Altera_Forum
Honored Contributor
@jmastron:
give me one or two days to write the results together. In the UDP stack the perfomance killers are UDP checksumcalculation and data transfer to the SMSC. - Altera_Forum
Honored Contributor
For the 5.0 release there is an errata specific to the lan91c111 and DMA:
http://www.altera.com/support/ip/processor...osii-50-er.html (http://www.altera.com/support/ip/processors/nios2/ips-niosii-50-er.html) I don't know if this also applied to earlier releases. What version are you using? Whats your HW configuration? - Altera_Forum
Honored Contributor
Don't know if this is useful or not but for a UDP datagram you don't have to
necessarily perform a checksum calculation, i.e. a UDP datagram with all zeroes checksum field is legal. I don't know if there's an option in the off the shelf software to support that, but it would speed up your throughput. Alan - Altera_Forum
Honored Contributor
@ tns1: I still use the 4.2 Version. I had no time to test the DMA controller with the SMSC chip but I'll test it next week. I read the errata for Quartus 5 and the SMSC.
For the 4.2 this problem is not mentioned. @amyler: I know the 0x0000 for UDP checksum is valid. But somehow I should check if the received data is okay. My HW checksum design works in the siumlation http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif . The real test will be next week.