Error compiling sdram.v

Dear all,

I recently created a new project in Verilog to test the Performance counter that seems not working in VHDL projects.

Whereas the verilog fast example distributed with Nios II works fine, the verilog standard and full_fledged examples fail to compile. The behavior is that the nios2 block is generated without problems by SOPC Builder, but when compiled in Quartus it gives the following error:

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...

Info: Using design file sdram.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project

Info: Found entity 1: sdram_input_efifo_module

Info: Found entity 2: sdram

Error: Can&#39;t process assignment. Attribute format is illegal -- parsing error (line 20). Use legal format for ALTERA_ATTRIBUTE assignment.

... (previous line repeated around 60 times)

Error: Can&#39;t elaborate user hierarchy "full_1s40:inst|sdram:the_sdram"

Error: Quartus II Analysis & Synthesis was unsuccessful. 65 errors, 244 warnings

Error: Processing ended: Fri Apr 01 10:41:18 2005

Error: Elapsed time: 00:00:40

Error: Quartus II Full Compilation was unsuccessful. 65 errors, 244 warnings[/b]

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The error line in sdram.v is something like

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output [ 31: 0 ] za_data;[/b]

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does anyone had the same error before?

Paolo