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Altera_Forum's avatar
Altera_Forum
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21 years ago

Error compiling sdram.v

Dear all, I recently created a new project in Verilog to test the Performance counter that seems not working in VHDL projects. Whereas the verilog fast example distributed with Nios II wor...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Yes, me!

In the same file!

Altera support couldn't help.

You need to open sdram.v with notepad (you will see more than in quartus,..... (!) )

this is the wrong line for my case: 

  reg      za_data /* synthesis ALTERA_ATTRIBUTE = FAST_INPUT_REGISTER=ON */;

you need to manually add the " : 

  reg      za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;

...after every sopc builder generation.

Don't ask why...

ciao

Marco