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Altera_Forum's avatar
Altera_Forum
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20 years ago

EPCS can't be THIS slow

I used the CycloneII dev-kit from altera for a project with uCLinux and a NiosII. To save some $$ I'm trying to configure the FPGA from the EPCS64 and load the kernel from the same EPCS64 thus eliminating the need for an extra ROM chip.

The FPGA get's configured correctly but the kernel takes ages (ok not ages but a couple of minutes(!!)) to load.

When booting the kernel from flash it is loaded in a few seconds (1 or 2 ...). I knew it would be slower but I'm pretty sure I made a mistake somewere 'cause this is just tooo slow.

Another thing that puzzles me is that the kernel boots halfway in about two minutes and then after 2 more minutes it&#39;s reloaded again (from the beginning, it doesn&#39;t continue where it was) and completes the boot sequence. From then on the system runs like it used to http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/ohmy.gif

Please tell me I did something wrong!

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi wgoossens,

    1. Did you select the fast mode for EPCS? with hardwire mode select pins?

    2. You should try boot from on chip memory, copy(or decompress) EPCS data to dram,

    then boot linux out of dram. Running directly on EPCS is very slow.

    Hippo
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Thank you for the reply,

    1. I&#39;m not sure. I use the CycloneII dev-kit with the components as created by Altera. I&#39;m lokking into it...

    2. If I understand it correctly I am doing excatly that. The code I used to program the EPCS is: 

    sof2flash --input=/cygdrive/t/CSC/Lusdetector_onderzoek_PV04900/03-0032-1_Lusdetector_usb_noFlash/fpga/standard.sof --output=standard.flash --epcs
elf2flash --epcs --after=standard.flash --input=../kits/nios2/bin/eclipse/workspace/kernel_no_flash/build/vmlinux --output=vmlinux.flash --boot=boot_loader_epcs.srec --end=0x3ffffff
nios2-flash-programmer --epcs --sof=altera_nios_dev_board_cyclone_2c35.sof --input=standard.flash
nios2-flash-programmer --epcs --sof=altera_nios_dev_board_cyclone_2c35.sof --input=vmlinux.flash --relocate

    from the documentation I thought the bootloader I include when generating the vmlinux.flash file sits in the first 1K (which is directly accesable) and copies the vmlinux to ram and jumps to the start-address.
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    The EPCS devices are extremely slow. I program them on a daily basis. In addition, booting from an EPCS device is not supported on all devices (i.e. the Stratix II). So for compatibility reasons you may want to avoid doing this anyway.

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi wgoossens,

    Check the epcs_controller definition in your ptf file for the "extradelay" parameter.

    You probably don&#39;t want it set to "1" ... it will signficantly affect your programming

    and boot times.

    Here are some related threads:

    http://forum.niosforum.com/forum/index.php...wtopic=2365&hl= (http://forum.niosforum.com/forum/index.php?showtopic=2365&hl=)

    http://forum.niosforum.com/forum/index.php...wtopic=2280&hl= (http://forum.niosforum.com/forum/index.php?showtopic=2280&hl=)

    http://forum.niosforum.com/forum/index.php...epcs_controller (http://forum.niosforum.com/forum/index.php?showtopic=1737&hl=epcs_controller)

    Regards,

    --Scott
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi wgoossens,

    Sorry, forgot about this one:

    > from the documentation I thought the bootloader I include when generating the

    > vmlinux.flash file sits in the first 1K (which is directly accesable) and copies the

    > vmlinux to ram and jumps to the start-address.

    You shouldn&#39;t need the bootloader at all when you&#39;re booting from the epcs device.

    The code in the epcs controller peripheral&#39;s on chip memory will search for the end

    of your configuration data, then load each section to the appropriate address.

    Regards,

    --Scott
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi Scott,

    I&#39;m at home now but couldn&#39;t stop thinking about the problem (I know, laugh as loud as you like) so I couldn&#39;t help but reading the forums....

    First of: Thanks for those links you provided I think that excatly adresses my problem. I&#39;ll try it as soon as possible. I&#39;ll come in early tomorrow to try it out http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

    I&#39;ll try and leave the bootloader out of the flash file &#39;cause what I now had was probably data from EPCS that got unpacked to RAM where the "second" bootloader kicked in to unpack my kernel from EPCS to RAM.... combine that with a EXTRA_DELAY parameter and you&#39;ve got my weird problem...

    @jakobjones: It&#39;s not a big deal if the boot-time is a bit higher (but not minute)... And you know how managers are: "Hey don&#39;t you think you can loose the onboard ROM? That would save us a lot of money!" So I have to work with a slow EPSC http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

    Thanks all!

    Walter Goossens
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    I&#39;m happy to announce that an upgrade to quartus 5.1 and NiosII 5.1 gave me a speedup of about 18000% !

    My boot time went from 180 seconds (I measured this morning) to under 1 second!!

    That&#39;s more like it!

    Thanks all for helping me out!
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Scott,

    I have the same problem here but it's slightly different.

    I am having Nios II system where the FPGA configuration data and Nios II software boot up from EPCS and run from my SRAM on custom board having a serial flash, SRAM and a small EEPROM. When the system boot up, Nios II CPU starts to run from SRAM and the first thing it does is it sets up some data in the EEPROM. My problem is that the time taken for the data to transfer from serial flash to SRAM is rather long and then the processor hangs somewhere as it doesn't write to EEPROM.

    When you say checking the extradelay for EPCS module for '0', may I know should I also ensure that the extradelay for SPI module (EEPROM) to be '0' as well? I have 3 SPI(s) in system. All are set to '1'. Does it affect?

    Thanks.

    Carid
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Probably worth starting a new thread for this rather than continuing a 5 year old thread that ended with an "upgrade" to Quartus 5.1