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Altera_Forum's avatar
Altera_Forum
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20 years ago

EPCS can't be THIS slow

I used the CycloneII dev-kit from altera for a project with uCLinux and a NiosII. To save some $$ I'm trying to configure the FPGA from the EPCS64 and load the kernel from the same EPCS64 thus el...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi Scott,

I have the same problem here but it's slightly different.

I am having Nios II system where the FPGA configuration data and Nios II software boot up from EPCS and run from my SRAM on custom board having a serial flash, SRAM and a small EEPROM. When the system boot up, Nios II CPU starts to run from SRAM and the first thing it does is it sets up some data in the EEPROM. My problem is that the time taken for the data to transfer from serial flash to SRAM is rather long and then the processor hangs somewhere as it doesn't write to EEPROM.

When you say checking the extradelay for EPCS module for '0', may I know should I also ensure that the extradelay for SPI module (EEPROM) to be '0' as well? I have 3 SPI(s) in system. All are set to '1'. Does it affect?

Thanks.

Carid