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Altera_Forum
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10 years ago

EPCQ Bootloader problems

Quartus 15.0, Cyclone V design

I'm booting the FPGA from a Micron N25Q128 SPI flash and am trying to transition my NIOS to boot from SPI flash instead of onchip RAM. I've read all of the app notes, white papers, etc. that talk about booting from EPCQ flash and have followed the instructions to the best of my knowledge, but I'm seeing weird results.

My NIOS design currently includes a DDR3 controller (which seems to be working fine for the original design), a Serial Flash Controller (SFC), UART, sysid and timer. The NIOS points to SFC with offset 0x800000 for the reset vector and to DDR with offset 0x20 for the exception vector. I generate HDL in QSYS, no problems.

In Eclispe I build a BSP for the project and set all the linker sections to point to DDR, then generate the BSP. I clean build the application and Make Targets/Build/mem_init_generate.

I compile the Quartus project with no errors.

I convert programming files and build a JIC image that includes the SOF (offset 0x0) and the SFC.HEX images (offset 0x800000).

I launch the Quartus Programmer and load the JIC image into my flash device. I verify the flash just to make sure the image is correct.

When I reboot using the new image, the FPGA comes up but the NIOS does not appear to be functioning (I do not see the messages that I expect on the UART console port). When I reboot a second time I find that the image in flash has become corrupted and the FPGA will no longer boot.

If I download the SOF file directly to the FPGA through the JTAG port and launch a debug session in Eclipse (which writes the application code directly to DDR) everything works as expected. I've been chasing this for most of the week and have run out of ideas.

Any suggestions?

Michael

13 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thanks, Taz.

    The thread you mentioned talks about using the older EPCS controller but I didn't see any new information.

    FWIW I have setup a project for the Cyclone V GX Starter Kit (https://www.altera.com/products/boards_and_kits/dev-kits/partners/kit-terasic-cyclone-v-gx-starter.html) and have not been able to make it work either. That board uses the EPCQ256 and a different set of DDR chips, but is very similar to my own board in most respects. I do not see the flash data corruption on the starter kit, but I never see the NIOS boot as it should.

    Michael
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The last time I used the EPCS-Core was on an own Cyclone IV-Board with great success.

    I am not sure if it is suitable for a Cyclone V...

    The last thing I know about Cyclone V, but it was with Quartus 13.1 to 14.1, where I thought I had the same problem. I had hoped, the problems would be gone with 15.0 ?!

    Have you tested all kind of cores from Altera related to EPCS/Q-Boot of the NIOS?

    If yes, please try to fill out an official Service-Request at Altera.

    Kind regards
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Solution:

    I opened an SR on this topic and got my local FAE from Arrow involved as well. The FAE discovered that the NIOS II/e will not boot from the serial flash controller (Quartus 15.0) and the work-around is to use the NIOS II/f instead. I posted this information to the SR and asked Altera to update the documentation to reflect this limitation, but I thought I would post the information here as well so that it shows up on Google searches.

    Michael
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    No, the EPCQ is limited to 25 MHz and I'm running the NIOS at 100 MHz.

    Michael
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Assuming you are using Qsys, for the nios II/e case, can you switch the default clock crossing adapter type from Handshake to FIFO in the "Interconnect Requirements" page then generate HDL and recompile in Quartus. Retry your test again? I think it is some issue with the clock crossing adapter.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I reverted to the NIOS II/e and made the change you suggested to the default clock crossing adapter and recompiled. The behavior is as before - the FPGA boots the new image but the NIOS does not boot.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I guess it is not related to the clock crossing. Now, I found something else that is may be similar:

    http://www.alteraforum.com/forum/showthread.php?t=47681

    In the above thread, Steve observed that Nios fails to boot from flash at power-on. But subsequent FPGA reset allowed the Nios to boot correctly. In his finding, he found that the Nios processor started reading from the flash without complying to the flash minimum reset time after power-on. He made modification to the arbitration logic to delay the grant signal banck to Nios to make his design work.

    Can you try to delay the grant signal back to the Nios processor? I can't tag Steve here for comment but will ask him to for more information on adding the delays.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi mellis,

    I have identified the same behavior with Quartus version 15.1. (stratix iv gx) In case of Nios II/f the Nios application is booting from EPCS64. If I change in QSYS to Nios II/e just the FPGA configuration is loaded after power on. I'm using the serial flash controller and the method described in that wiki:

    http://www.alterawiki.com/wiki/booting_nios_from_serial_flash_with_the_new_altera_serial_flash_controller

    Nios IIGen2 as well as Gen1 (claasic) systems have that problem. Furthermore it does'nt matter if the Serial Flash Controller or the EPCS legacy controller is used. Just with Quartus 13.1 and below booting Nios (with the EPCS controller) from EPCS works fine.

    I don't have a solution but spending the 500-600 ALMs more for Nios II/f.

    Jens