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Honored Contributor
Honored ContributorEPCQ Bootloader problems
Quartus 15.0, Cyclone V design I'm booting the FPGA from a Micron N25Q128 SPI flash and am trying to transition my NIOS to boot from SPI flash instead of onchip RAM. I've read all of the app n...
Altera_ForumHonored Contributor
Honored ContributorAssuming you are using Qsys, for the nios II/e case, can you switch the default clock crossing adapter type from Handshake to FIFO in the "Interconnect Requirements" page then generate HDL and recompile in Quartus. Retry your test again? I think it is some issue with the clock crossing adapter.
