Forum Discussion
Honored ContributorDownloading ELF Process failed
PC:
Altera 10.0sp1, Nios IDE10.0sp1; Win7 32bit ultimate Chinese edition ---------------------------------------------------------------- when i use on chip memory,every goes well.but when i use sdram controller,try many times,the same error. Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Processor is already paused Reading System ID at address 0x00000000: verified Initializing CPU cache (if present) OK Downloading 01000000 ( 0%) Downloading 01003D58 (63%) Downloaded 16KB in 0.2s (80.0KB/s) Verifying 01000000 ( 0%) Verify failed between address 0x1000000 and 0x1002723 Leaving target processor paused ------------------------------------- the log: Downloading ELF Process failed,An exception stack trace is not available. Failed Executing: [nios2-download, '--cable=USB-Blaster on localhost [USB-0]', --device=1, --instance=0, CPU master group not set. CPU architecture type not set. ... --------------------------------- what should i do?thank you !24 Replies
Altera_ForumIn the license set up I can see all the mega core functions as well. That means it picks my license correctly. And .sof file is also correct. Following is my full error message.
"Launching 'new configuration has encountered a problem. Downloading ELF Process failed.'" Thanks Daixiwen.- Altera_Forum
There is no error there, Eclipse isn't even trying to upload the software. That's very strange. Are you sure it isn't saying something else after that?
- Altera_Forum--- Quote Start --- Please exit Nios SBT, then delete .megadata folder in the same directory with your software and bsp projects. It works with me all the time. --- Quote End --- HOLLY MOLLY. This was the ONLY advice that worked! I was almost losing my head but as AR that I am, finally I crossed paths with this. It just worked!
- Altera_Forum
I received same massage,“Launching New Configuration has encountered a problem”, "Downloading ELF Process failed" and I solved by check Pin Assignment . In Qsys SDRAM name SDRAM but pin name is DE1 is DRAM. I changed and OK. I hope it help you.
- Altera_Forum
I solved it by checking all the connections in Qsys but was a bit disappointed because of the random errors keep popping up randomly and disappearing after restarting the IDE.
- Altera_Forum
Did your design meet timing? Are you using SDRAM?
- Altera_Forum
Hi
My design does not contain SDRAM. Its a simple design. Now I have changed the quartus ii version to 10.0. Design is done in SOPC. Still no success.I have attached here. Thanks Rupok - Altera_Forum
Can you attached your Qsys design and Quartus project? I can't really see from your thumbnails (blurry)
- Altera_Forum
Hi
I have attached the a zip file here. File size becomes too large so I could not zipped all file. But you will find all necessary files here. I have tried here with quartus 13.1 version. All version must not create problem and I have tried several times and found most of the time its the matter of On_chip_memory2 although the connection seems working. Looking forward to hearing from you soon. I would be really happy to know where I am mistaking. Thanks Rupok - Altera_Forum
Your Qsys system looks fine.
However, I noticed that the CLOCK_50 pin assignment is missing from the Nios_led.qsf. You will need to set the pin to the correct clock pin on CYCLONE IV E. Also you can try to run simulation as well.
