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Hi,
Maybe you can escalate the issue to Altera Support. If you're still fresh about the issue, you may send them the archive of your project for them to "reproduce".
Hopefully this will solve the bug.
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That what I probably have to do, but I am too lazy to start answering questions like "Did you try 10.0 SP22?, Did you reproduce in latest hottest 10.0.0 preliminary beta?" etc, etc....
Now to the good news. We found a workaround.
Just insert Avalon-MM pipeline bridge without burst support between in between NiosII CPU and cfi flash. The bridge converts single-word burst writes coming from the CPU which are triggering the bug into regular 32-bit writes with properly set byteenables that altera_avalon_cfi_flash module capable to deal with.
That's actually was easy. Doesn't compare with obscure, hard to reproduce, DDR2 on Arria2GX problems that I am fighting for majority of the recent week :cry:
Honored Contributor
