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Half a year later.
Today we encountered exactly the same SOPC bug.
Unlike your case, for us Data Cache Burst is important since we plan for heavy use of DDR SDRAM. So your workaround wouldn't work for us.
Of course, we can manually edit SOPC builder generated file multiplying chip select by byteenable, but it's ugly and doesn't fit our development process.
Is there a hope for actual bug fix?
Or, may be, less ugly workaround that will allow us to use both dcache bursts and cfi flash at the same NiosII CPU?
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Hi,
Maybe you can escalate the issue to Altera Support. If you're still fresh about the issue, you may send them the archive of your project for them to "reproduce".
Hopefully this will solve the bug.
Honored Contributor
