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Altera_Forum's avatar
Altera_Forum
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18 years ago

does the inital uclinux design ...

Moin,

My current HW is a CyclonII NIOS devboard; i started with loading the board with the standard.sof example design and the tryOutuClinux. Everything worked OK. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

Next, i&#39;ve downloaded and built the uClinuxDist like explained in the wiki. Seems to compile without errors; at least i have a zImage lying around at the ususal place with a sensible size.

During the build i had to do a 

make vendor_hwselect SYSPTF=~/std_2C35.ptf

there - as also stated in the wiki - http://nioswiki.jot.com/wikihome/operating...x/linuxhwselect (http://nioswiki.jot.com/wikihome/operatingsystems/%c2%b5clinux/linuxhwselect)

i had no other choice than altera_avalon_cfi_flash, when asked where to upload the kernel.

Now i&#39;m unsure, if my brandnew zImage will overwrite the contents of any flashmemories located on the devboard, if loaded. Is that the case?

If yes - what do i have to change to get an Image like the tryOutuClinux, running completly from RAM, not altering any flashes?

Another Question - slightly off topic:

Looks like i have severe problems doing own designs with the SOPC, wich contain DDR-SDRAM. I&#39;m really confused by the error messages, don&#39;t know exactly which pins have to be assigned manually, which names of signals must not be changed,stuff like this.

Is it just the normal "beginners-pain-in-the-a*" or do i read not enough documentation?

Cheers,

WK

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Don&#39;t worry about the cfi flash. It is actually dummy, because we use initramfs instead of romfs. So the zImage is built to be run from SDRAM. There is no flash programming required, unless you want it.

    About the DDR SDRAM, you may post it on the general discussion forum. You MUST set your board trace delay in the DDR workbench. After you generate in SOPC builder, a contrain scipt will be created and the quartus will automatically run it. After that, you will still need to place the other DDR pins which are not placed by the contrain script, namely clock,address, ras/cas etc. There are some contrains on these SSTL2 pin placements. You should read the spec of your fpga to find them.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hello,

    Thanks for the information. The first "self" compiled uClinux seems to run http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

    Also the DDR-SDRAM problem seems to be solved. I was just trying do do a "design" on the CyclonII-NIOS Evalboard, so track lengths etc. were not the issue.

    It was the naming of the signals from the SOPC to the pins of the device, which caused the error-msgs. When the pins of the device have names like e.g.: ddr_a_from_the_ddr_sdram_0[0], then i get the errors, when the pins have names like ddr_a[0] then the design compiles.

    Cheers,

    WK