Honored Contributor
Honored ContributorDon't worry about the cfi flash. It is actually dummy, because we use initramfs instead of romfs. So the zImage is built to be run from SDRAM. There is no flash programming required, unless you want it.
About the DDR SDRAM, you may post it on the general discussion forum. You MUST set your board trace delay in the DDR workbench. After you generate in SOPC builder, a contrain scipt will be created and the quartus will automatically run it. After that, you will still need to place the other DDR pins which are not placed by the contrain script, namely clock,address, ras/cas etc. There are some contrains on these SSTL2 pin placements. You should read the spec of your fpga to find them.
