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fpgaSoft's avatar
fpgaSoft
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2 years ago

DMA with NIOSII

Hi, I am using a Cyclone 10 FPGA with NIOS for a project and I am running into a few problems with the DMA IP block. The DMA block in question is the Modular Scatter-gather DMA IP, in memory-mapped ...
Nios Cpu
KellyJialin_Goh's avatar
KellyJialin_Goh
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2 years ago

Hi,

Any updates from your end whether the information provided was useful?


Thank you.


Regards,

Kelly


fpgaSoft's avatar
fpgaSoft
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2 years ago

Hi Kelly,

sadly the information didnt help as to why the data is being sent out before the VALID line is asserted. I have ended up going back to using the memory-mapped to memory-mapped version of the DMA. However the streaming version does look more appropriate for my design so it would be good to know why it doesnt appear to be working properly

Best regards