DMA with NIOSII
Hi, I am using a Cyclone 10 FPGA with NIOS for a project and I am running into a few problems with the DMA IP block.
The DMA block in question is the Modular Scatter-gather DMA IP, in memory-mapped to stream mode.
I have the stream output going into signal tap to look at the data. Some of the time the data looks ok. i.e the data is available as soon as the source_valid goes high, the VALID is high for the 4x32 bit words I am sending.
However every now and then VALID is only high for one of the blocks of data, some are before it. I could be doing something wrong but according to the IP, VALID should be rasied when there is valid data & not after.
Is there something I am doing wrong? Or is this actually expected behaviour? If so how do I account for that, given I only the limited lines i have out of the block?
Best regards