Altera_Forum
Honored Contributor
19 years agoDM9000A Ethernet and the 25 Mhz Clock
I realise that the DM9000 chip needs a 25 Mhz clock from a PLL, but I'm confused about how to actually deliver it and handle the other signals.
I would think you could use a PLL like so: pll: sdram_pll PORT MAP (CLOCK_50, DRAM_CLK, ENET_CLK); Which would connect the -3 ns output of the PLL to the SDRAM and the divided-by-2 output to the Ethernet chip. The DE2_NET example, however, has the following port maps: // the_DM9000A
.ENET_CLK_from_the_DM9000A(ENET_CLK),
....
.iOSC_50_to_the_DM9000A(CLOCK_50), There is also a PLL which has a 25 Mhz output, but I can't find a place where it connects to the Ethernet chip. If somebody can clear this up it would be much appreciated.