DM9000A Ethernet and the 25 Mhz Clock

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originally posted by benway@Mar 17 2007, 05:49 PM

i realise that the dm9000 chip needs a 25 mhz clock from a pll, but i'm confused about how to actually deliver it and handle the other signals.

i would think you could use a pll like so:

    pll: sdram_pll port map (clock_50, dram_clk, enet_clk);

which would connect the -3 ns output of the pll to the sdram and the divided-by-2 output to the ethernet chip.

the de2_net example, however, has the following port maps:

               // the_dm9000a
   .enet_clk_from_the_dm9000a(enet_clk),
                 ....
   .iosc_50_to_the_dm9000a(clock_50),

there is also a pll which has a 25 mhz output, but i can't find a place where it connects to the ethernet chip. if somebody can clear this up it would be much appreciated.

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In the DE2_NET project, the ENET_CLK signal is generated in the DMA9000A_IF.v file, by using a simple divider from a 50Mhz signal to get a 25MHz signal.

I agree that it is better to use a PLL to generate the ENET_CLK signal. So you can probably go with PLL code you have.