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NIJGNAS's avatar
NIJGNAS
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3 months ago

DK-DEV-AGI027-RA: JTAG chain broken after Nios V Hello, FPGA recovery fails

Hello, I am using the following board and host environment: Board: Agilex 7 FPGA I-Series Development Kit, DK-DEV-AGI027-RA Serial number: 8100604 Quartus Prime Pro: 25.3.1 Host OS: Windows 11 ...
Nios Architecture
Nios Cpu
SteveK_Arrow's avatar
SteveK_Arrow
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3 months ago

Hi 

Can you provide more details regarding the Nios V Hello tutorial modifications, including the SmartVID changes? The issue seems to imply that either the FPGA was damaged or is not being powered to its required core voltage.

Thanks

  • NIJGNAS's avatar
    NIJGNAS
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    3 months ago

    Hi,

    Sure. I followed the DK-DEV-AGI027-RA dev kit documentation and only changed the configuration scheme, SmartVID (PMBus) related settings, and the clock/reset pin constraints when porting the Nios V Hello design.

    I am attaching screenshots of:

    • Device and Pin Options - Configuration
    • Configuration Pin Options
    • Device and Pin Options - Power Management and VID

    1) Device and Pin Options settings

    SectionSettingValue
    ConfigurationConfiguration schemeAVST x8
    ConfigurationVID mode of operationPMBus Master
    Configuration Pin OptionsUSE PWRMGT_SCL outputEnabled, SDM_IO0
    Configuration Pin OptionsUSE PWRMGT_SDA outputEnabled, SDM_IO12
    Configuration Pin OptionsUSE CONF_DONE outputEnabled, SDM_IO16
    Configuration Pin OptionsOther pins (PWRMGT_ALERT, INIT_DONE, etc.)Not enabled
    Power Management and VIDBus speed mode100 KHz
    Power Management and VIDSlave device typeOther
    Power Management and VIDNumber of slave devices1
    Power Management and VIDPMBus device 0 slave address47
    Power Management and VIDEnable PAGE commandOff (unchecked)

     

    2) Clock and reset constraints used

    # Reset

    set_location_assignment PIN_D36 -to reset_reset_n

    set_instance_assignment -name IO_STANDARD "1.2-V" -to reset_reset_n

    # Clock (differential)

    set_location_assignment PIN_N45 -to clk_clk

    set_location_assignment PIN_L46 -to clk_clk(n)

    set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to clk_clk

    These settings allowed the design to program successfully and print the "Hello" message once. After that first run, JTAG Auto Detect started failing with the UNKNOWN devices and the same JTAG chain error messages as previously posted.

    Thanks.

    • SteveK_Arrow's avatar
      SteveK_Arrow
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      3 months ago

      Hi

      I think it would be interesting to see what happens if the SDM I2C controller is disabled. The SDM controller is responsible for the SmartVID function and the JTAG chain.

      Set SW4 [1:4] to OFF/OFF/ON/OFF, where OFF is open and ON is closed.  (Table 4 of the Development Kit User Guide)

      Thanks

       

  • NIJGNAS's avatar
    NIJGNAS
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    3 months ago

    -duplication-

    • BoonBengT_Altera's avatar
      BoonBengT_Altera
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      1 month ago

      Hi NIJGNAS,

       

      Greetings, as we do not receive any further clarification/updates on the matter, hence would assume challenge are overcome. We will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

      Thank you for engaging with us!

       

      Best regards,
      Altera Technical Support