De2 board Key0 problem

Are you using Verilog, VHDL or Block Diagram?

Verilog Solution (Top level module):

module Top (
CLOCK_50,
KEY
);
input CLOCK_50;
input  KEY;
nios_system NIOSII (
.clk (CLOCK_50),
.reset_n (KEY)
);
endmodule

Necessary pin assignments:

CLOCK_50 = PIN_N2

KEY[0] = PIN_G26

The code assumes that your SOPC Builder system is called nios_system. Also, you will have to add signals for all the other components in your system.

A second option is to make the nios_system the top level module and assign

clk = PIN_N2

reset_n = PIN_G26

in the pin assignment editor.

As for the choice of processors, you can use any version which meets the needs of your application. I like the economy version for its size and lack of caches, but it can be too slow for some applications.

- Blair

Thanks a lot.

I am writing a uc/os-II program running on nios2 core.

what I am using is in the directory

DE2_demonstrations\SOPC_Builder\Reference_Design\DE2_NIOS

In DE2_NIOS.v I find this line

Reset_Delay delay1 (.iRST(KEY[0]),.iCLK(CLOCK_50),.oRESET(CPU_RESET));

Perhaps that's the reason,I wonder if I can modify that via SOPC Builder.

No, I think that it should work fine. Just that the CPU_RESET signal should go to the reset_n signal of the nios_system, instead of the KEY[0] signal as I previously indicated.

Also, that can not modify this in SOPC Builder, but I can be modify in Quartus II by directly editting the DE2_NIOS.v file.

- Blair