DE2 board. Flash and sram with NIOS

Both connect to tri_state_bridge_data.

I think your flash data port is only 8 bits wide: connect it to tri_state_bridge_data[7..0].

The other data lines connect only to sram

tri_state_bridge_data[7..0] to flash_data[7..0]

tri_state_bridge_data[15..8] to sram_data[15..8]

but what with sram_data[7..0] ?

You have misunderstood.

tri_state_bridge_data[7..0] to flash_data[7..0]

tri_state_bridge_data[15..0] to sram_data[15..0]

They are multiplexed. Tristate bus will automatically drive oe and cs pins to enable only the correct chip when you rd or wr on its address range.

I did like you're saying but I got error:

http://aix.vot.pl/nios/nios_error.jpeg

Sorry. It was me the one who misunderstood.

I wrongly assumed flash_data[7..0] and sram_data[7..0] actually were the same pins, since this is what I have on my board.

I think the solution in your case is to instantiate in sopc builder TWO tristate buses: one for sram and one for flash.

Now it works. Thanks.

In others words, tri state bridge we can use with slave devices when they have the same pins on the board?

Actually in your case there's no need of a tristate bus, since you have a single device and data pins don't need to be tristated. This is mandatory when you have multiple devices using the same data lines.

Connecting to sopc tristate bus makes sense because you easily have all connection signals ready without requiring any glue logic or a specific sopc module. The best implementation would be building a custom async memory interface sopc module without the unnecessary tristate logic.