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Honored Contributor
Honored ContributorDE2-115: Problem - ISP1362 Does Not Work
Hi guys,
I am using DE2-115 board configured with SOPC file from included DE2-115 CD (DE2_115_NIOS_DEVICE_LED). I removed all components except the following: - pll - jtag_uart - cpu - onchip_memory - sdram - clock_crossing_io - timer - sysid - usb I made some changes on the remaining components as below (SOPC screenshot attached): 1. cpu - enable hardware divide - reset & exception vector: memory: sdram - include mmu - fast TLB miss exception vector: memory: onchip_memory - include tightly coupled instruction & data master ports 2. onchip_memory - enable dual port access - total memory size: 1024 bytes 3. usb - changed name to ISP1362 This is the content of DTS file generated:/*
* This devicetree is generated by sopc2dts
* Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
* in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>
*/
/dts-v1/;
/ {
model = "ALTR,DE2_115_SOPC";
compatible = "ALTR,DE2_115_SOPC";
# address-cells = < 1 >;
# size-cells = < 1 >;
cpus {
# address-cells = < 1 >;
# size-cells = < 0 >;
cpu: cpu@0x0 {
device_type = "cpu";
compatible = "ALTR,nios2-11.1";
reg = < 0x00000000 >;
interrupt-controller;
# interrupt-cells = < 1 >;
clock-frequency = < 100000000 >; /* embeddedsw.CMacro.CPU_FREQ type NUMBER */
dcache-line-size = < 32 >; /* embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER */
icache-line-size = < 32 >; /* embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER */
dcache-size = < 2048 >; /* embeddedsw.CMacro.DCACHE_SIZE type NUMBER */
icache-size = < 4096 >; /* embeddedsw.CMacro.ICACHE_SIZE type NUMBER */
ALTR,implementation = "fast"; /* embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING*/
ALTR,pid-num-bits = < 8 >; /* embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER */
ALTR,tlb-num-ways = < 16 >; /* embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER */
ALTR,tlb-num-entries = < 256 >; /* embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER */
ALTR,tlb-ptr-sz = < 8 >; /* embeddedsw.CMacro.TLB_PTR_SZ type NUMBER */
ALTR,has-div; /* embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT type NUMBER*/
ALTR,has-mul; /* embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER*/
ALTR,reset-addr = < 0xc0000000 >; /* embeddedsw.CMacro.RESET_ADDR type NUMBER */
ALTR,fast-tlb-miss-addr = < 0xc9001000 >; /* embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER */
ALTR,exception-addr = < 0xc0000020 >; /* embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER */
}; //end cpu@0x0 (cpu)
}; //end cpus
memory@0 {
device_type = "memory";
reg = < 0x00000000 0x08000000
0x09001000 0x00000400 >;
}; //end memory@0
sopc@0 {
ranges;
# address-cells = < 1 >;
# size-cells = < 1 >;
device_type = "soc";
compatible = "ALTR,avalon", "simple-bus";
bus-frequency = < 100000000 >;
clock_crossing_io: bridge@0x8000000 {
compatible = "ALTR,avalon-11.1", "simple-bus";
reg = < 0x08000000 0x00000040 >;
# address-cells = < 1 >;
# size-cells = < 1 >;
ranges = < 0x00000000 0x08000000 0x00000020
0x00000020 0x08000020 0x00000008 >;
timer: timer@0x0 {
compatible = "ALTR,timer-11.1", "ALTR,timer-1.0";
reg = < 0x00000000 0x00000020 >;
interrupt-parent = < &cpu >;
interrupts = < 0 >;
clock-frequency = < 10000000 >;
}; //end timer@0x0 (timer)
sysid: sysid@0x20 {
compatible = "ALTR,sysid-11.1", "ALTR,sysid-1.0";
reg = < 0x00000020 0x00000008 >;
}; //end sysid@0x20 (sysid)
}; //end bridge@0x8000000 (clock_crossing_io)
jtag_uart: serial@0x9001410 {
compatible = "ALTR,juart-11.1", "ALTR,juart-1.0";
reg = < 0x09001410 0x00000008 >;
interrupt-parent = < &cpu >;
interrupts = < 1 >;
}; //end serial@0x9001410 (jtag_uart)
pll: clock@0x9001400 {
compatible = "ALTR,pll-11.1", "ALTR,pll-1.0";
reg = < 0x09001400 0x00000010 >;
}; //end clock@0x9001400 (pll)
ISP1362: isp1362@0x9001418 {
compatible = "nxp,isp1362-1.0", "nxp,usb-isp1362";
reg = < 0x09001418 0x00000004
0x0900141C 0x00000004
0x09001420 0x00000004
0x09001424 0x00000004 >;
interrupt-parent = < &cpu >;
interrupts = < 2 3 >;
}; //end isp1362@0x9001418 (ISP1362)
}; //end sopc@0
chosen {
bootargs = "debug console=ttyAL0,115200";
}; //end chosen
};
