Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHi,
Thanks for your reply. I use the default hardware timing configured in the reference design. For ISP 1362: hc (connected to data master) Setup: 140ns Read wait: 50ns Write wait: 50ns Hold: 140ns dc (connected to data master) Setup: 150ns Read wait: 150ns Write wait: 150ns Hold: 150ns I did try to change all parameter values to 100ns as described in altera wiki, but still failed. For sdram: Clock frequency: 100MHz Clock phase shift: -65 deg Oh yes, there is 1 more thing. If I only use Nios II without MMU, and compiled using older version of Nios II Linux, the USB works properly. Any idea regarding this situation? Thanks! ^^ Regards, Gladion