Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

DE0-NIOS2 clock speed limit 50MHZ

Hi, have "problem". I have DE0 dev board. When I load NIOS2 to fpga and use 50MHz from on board sorce. It works. When I try to add pll 50MHz - > works. But if I use more then 50MHz (pll ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

I have used all pll types - it does not increase speed. Just give variation fort 10 ish mhz.

I have looked at recommendations, same result. What else could increase speed.

I use default constrains ( if the is any :) ). Should I apply custom constrains?

Sorry I am very new in FPGA design.

In reports I see that all slack's are positive, with back up.