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Honored Contributor
Honored ContributorDE0-NIOS2 clock speed limit 50MHZ
Hi, have "problem". I have DE0 dev board. When I load NIOS2 to fpga and use 50MHz from on board sorce. It works. When I try to add pll 50MHz - > works. But if I use more then 50MHz (pll ...
Altera_ForumHonored Contributor
Honored ContributorYou should check if the Timing analysis pass to look what is the maximum frequency allowed.
