Altera_Forum
Honored Contributor
19 years agoDDR SDRAM vs SSRAM
I've develop a project with 3 Nios II processors and 4 on-chip memories and mutexes. And I'm using a Development kit Cyclone II and Quartus and Nios IDE 5.0. Often in my code the processors need to verify the state of one or two variables in the shared on-chip memories. For example:
.... while(shared_memory->flag =! OK); (***) lock_mutex; read_and_write_data; unlock_mutex; .... So, the problem is that: The application only runs well if I store code (.text,.rodata,.rwdata,.heap,.stack) of the the processors in the DDR SDRAM and if I use standard processors. If I use fast processors or if I try to store code of two of these processors in the SSRAM, the application is paused in almost all the points where this kind of verifying (***) is made. No problems are displayed in Nios terminal when downloading codes. What is stranger is that data among processors are in fact sent and received by the others however it seems the processors are not being able to recognize that the state of a flag in a shared memory has been changed. I've just noticed that, when cpus paused, if I use the "step over" tool (in nios IDE debug perpective), sometimes, this condition (***) is successful verified and the execution go a head until another verification is necessary. I've just try also lock a mutex before make these verications but the problem remains. I can't understand that. Can't I store code in SSRAM? Why using nios/f processors provides me this problem? My goal using SSRAM and Nios /f is to reduce conflict among processors in access to code in just one memory device. Thanks a lot. mendonca.