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Altera_Forum
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19 years ago

DDR SDRAM vs SSRAM

I've develop a project with 3 Nios II processors and 4 on-chip memories and mutexes. And I'm using a Development kit Cyclone II and Quartus and Nios IDE 5.0. Often in my code the processors n...
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Altera_Forum
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19 years ago

Hi mendonca,

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originally posted by mendonca@Aug 17 2006, 08:56 AM

i've enjoyed your suggestion too much. can you send me a simple example of how can i use that opcode. i don't know it yet. or, maybe, the name of the header file where are declaring the routines i need to use. with this i suppose i can take more informations in nios ii software handbook.

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In the Nios II Software Developer's Handbook look at Chapter 7 Cache & Tightly-Coupled Memory. There is a section about Managing Cache in Multi-Master Systems. Cache bypassing is explained there.

Just another heretic thought: Have you connected your on-chip memory to all of your processors in sopc builder? If they aren't connected and you read from the address you get undefined results, maybe 0x00 or 0xff. 

while(shared_memory->flag != OK); (***)
lock_mutex;
read_and_write_data;
unlock_mutex;

btw, why do you check the flag before taking the (hardware) semaphore? The purpose of the semaphore is to synchronize access to shared memory. Why not use the api provided by Altera for the semaphore and leave the work to their code?

Regards,

Wolfgang