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tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
10 months ago

Hi

I managed to migrated it to our devkit and got it to ping.

Please find the attached.

Regards

Jingyang, Teh

  • Paul36's avatar
    Paul36
    Icon for New Contributor rankNew Contributor
    10 months ago

    Hi JingyangTeh,
    Thanks for your project.
    I wanted to double-check with you regarding the clk_enet_fpga_p pin (AB16). Can this pin be used as a normal I/O(configure normal I/O in your project)? On the schematic, it is marked as an LVDS differential pin. I previously configured it as LVDS, but it seems there is an error indicating that pin AB16 does not support the HSSI reference clock. Could you clarify this?



    Additionally, are there any special settings required when generating the BSP?

    For reference, I typically enable os_tmr_en and uc_tcp_ip, while leaving other settings at their default values.

    Thank you, and I look forward to your response!

    Best regards,

    Paul

    • Paul36's avatar
      Paul36
      Icon for New Contributor rankNew Contributor
      10 months ago

      Hi JingyangTeh,

      I have tried your project but it have the error 2010 that I checked that you have faced it before.

      and I checked the reset pin already there from the project that you sent to me.

      Just see any other think I am missing.

      Thanks

      Best regards,

      Paul