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Altera_Forum's avatar
Altera_Forum
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19 years ago

Cyclone - Fitting M4K blocks

I've been experimenting with using different cache sizes in the NIOS CPU.

There are sizes which don't compile under Quartus, for instance: 

Total Logic Elements - 5452 / 5980 (91%)
Total memory bits - 72960 / 92160 (79%)
...fitter reports:
Error: Selected device has 20 RAM location(s) of type M4K RAM.  However, the current design needs more than 20 to successfully fit

Therefore I have to select cache sizes that report "total memory bits" in the region of 65% (4064 Bytes unused), which appears to be a low percentage.

Is it possible to be able to harvest more memory bits?

Instruction Cache is 4kB

Data Cache is 1kB, line size of 4 bytes

The M4k block usage in the report is: 

cpu_0_dc_data_module -> 2
cpu_0_dc_tag_module -> 2
cpu_0_ic_data_module -> 8
cpu_0_ic_tag_module -> 1
cpu_0_bht_module -> 1
cpu_0_nios2_oci -> 2
cpu_0_register_bank_a_module -> 1
cpu_0_register_bank_b_module -> 1
(total 18)

What's the BHT and OCI?

Also - this is from the FIT file....the register banks and BHT look rather wasteful. 

+----------------------------+----------------------------+--------------------+-----+----------------------------+
; Implementation Port B Depth; Implementation Port B Width; Implementation Bits; M4Ks; MIF                        ;
+----------------------------+----------------------------+--------------------+-----+----------------------------+
; 256                        ; 2                         ; 512               ; 1  ; cpu_0_bht_ram.mif          ;
(data cache)
; 256                        ; 32                        ; 8192              ; 2  ; None                      ;
; 256                        ; 22                        ; 5632              ; 2  ; cpu_0_dc_tag_ram.mif      ;
(instruction cache)
; 1024                       ; 32                        ; 32768             ; 8  ; None                      ;
; 128                        ; 18                        ; 2304              ; 1  ; cpu_0_ic_tag_ram.mif      ;
; 256                        ; 32                        ; 8192              ; 2  ; cpu_0_ociram_default_conten;
; 32                         ; 32                        ; 1024              ; 1  ; cpu_0_rf_ram_a.mif        ;
; 32                         ; 32                        ; 1024              ; 1  ; cpu_0_rf_ram_b.mif        ;
+----------------------------+----------------------------+--------------------+-----+----------------------------+

Presumably, doubling the data cache line size would halve the number of entries thus saving one block.

Are the .MIF files used to implement look-up tables?

RAM occupies space $080000 to $0FFFFF

(ROM also occupies space $100000 to $1FFFFF but code is not executed from it)

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    By changing the data cache line size to 16, I could change the data cache size to 2KB: 

    ; Total logic elements; 5,641 / 5,980 ( 94 % )                      ;
; Total memory bits    ; 65,024 / 92,160 ( 71 % )                    ;
; M4Ks                                      ; 20 / 20 ( 100 % )                    ;
+---------------------------+---------------------------+-------------------+----+---------------------------------+
; Implementation Port B Depth; Implementatin Port B Width; Implementatin Bits;M4Ks; MIF                              ;
+---------------------------+---------------------------+-------------------+----+---------------------------------+
; 256                        ; 2                         ; 512               ; 1  ; cpu_0_bht_ram.mif                ;
(data cache)
; 512                        ; 32                        ; 16384             ; 4  ; None                            ;
; 128                        ; 21                        ; 2688              ; 1  ; cpu_0_dc_tag_ram.mif            ;
; 4                        ; 32                      ; 128              ; 1; None                          ;
(instruction cache)
; 1024                       ; 32                        ; 32768             ; 8  ; None                            ;
; 128                        ; 18                        ; 2304              ; 1  ; cpu_0_ic_tag_ram.mif            ;
; 256                        ; 32                        ; 8192              ; 2  ; cpu_0_ociram_default_contents.mif;
; 32                         ; 32                        ; 1024              ; 1  ; cpu_0_rf_ram_a.mif              ;
; 32                         ; 32                        ; 1024              ; 1  ; cpu_0_rf_ram_b.mif              ;
+---------------------------+---------------------------+-------------------+----+---------------------------------+

    A "dc_victim_module" has appeared in this one (using 128 bits). What's that?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    I suggest experimenting, since I do not know if Altera provides any instructions on how to optimize cache size.

    I had to remove the debug module and the epcs-controler, each consuming only a single M4K and I was able to set 8/4 cache on an EP2C8 chip (36 M4K blocks). So try some modifications. Try removing other unnecessary M4K consumers.

    The BHT and OCI are probably some tables with addresses connecting the main memory with cache. There is a lot of logic beside around the cache to make it work.

    IzI
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    BHT is the branch history table. It is used in the Nios II/f for dynamic branch prediction and is unrelated to the caches.