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Altera_Forum
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19 years ago

Cyclone - Fitting M4K blocks

I've been experimenting with using different cache sizes in the NIOS CPU. There are sizes which don't compile under Quartus, for instance: Total Logic Elements - 5452 / 5980 (91%...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

I suggest experimenting, since I do not know if Altera provides any instructions on how to optimize cache size.

I had to remove the debug module and the epcs-controler, each consuming only a single M4K and I was able to set 8/4 cache on an EP2C8 chip (36 M4K blocks). So try some modifications. Try removing other unnecessary M4K consumers.

The BHT and OCI are probably some tables with addresses connecting the main memory with cache. There is a lot of logic beside around the cache to make it work.

IzI