Cyclone - Fitting M4K blocks

I suggest experimenting, since I do not know if Altera provides any instructions on how to optimize cache size.

I had to remove the debug module and the epcs-controler, each consuming only a single M4K and I was able to set 8/4 cache on an EP2C8 chip (36 M4K blocks). So try some modifications. Try removing other unnecessary M4K consumers.

The BHT and OCI are probably some tables with addresses connecting the main memory with cache. There is a lot of logic beside around the cache to make it work.

IzI