I would have thought it was best to generate the 'done' signal from within your own logic.
After all you will have an internal signal (or can easily generate one) that is asserted when the result is available.
I thought I remembered there being an option for 'fixed length', maybe it can only be set when you create the component.
I do remember that it wasn't obvious how to edit the details - IIRC you have to run the component editor.
There were certainly a pile of bugs in the version of the sopc builder I was using - it got very confused if you added and removed custom instructions from the cpu itself.
All not helped by the only examples just describing how to tick the boxes to include the FP instructions.