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Altera_Forum
Honored Contributor
Honored ContributorCustom instruction
Hi, How can I control the clock enable and other signals for implemented custom instruction with hardware inside the NIOS II (sequential)? Maybe some more examples have Altera (not only combina...
Altera_ForumHonored Contributor
Honored ContributorA lot of the logic of the custom instruction interface can be seen in the RTL viewer.
I suspect that the 'clock enable' is the signal used to stop the cpu during pipeline stalls - so a variable length custom instruction must assert 'done' while clock enable is asserted (but need not otherwise look at it). A fixed length instruction (where the interface counts the clocks for you) will almost certainly have to apply the clock enable to everything.
