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Nikitha_Sree's avatar
Nikitha_Sree
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2 years ago

Creating a Ibex component in platform designer on Arria 10 FPGA development board

Hello Everyone, I'am trying to create an Ibex component in the platform designer and trying to connect JTAG UART IP, On chip memory IP to that am facing the below connection errors : Error: ris...
Nios Cpu
Nikitha_Sree's avatar
Nikitha_Sree
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2 years ago

Hi TingJiangT ,

Thanks for the response.

Under the System --> Remove Dangling Connections is not been highlighted for selecting.

Please find the screenshot for reference.

Can you give me some information regarding the timer_sw_agent ,dm_agent in the Nios V Processor IP and there signals.

Thanks

Nikitha

yanlalalala's avatar
yanlalalala
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1 year ago

Hi Nikitha,

According to your snapshot, you are using a custom component called myriscv as the soft processor right? I'm sorry to say that we cannot automatically remove dangling connections for custom components.

If you want to modify your component refer to Nios V Processor, you can use this user guide 4. Nios® V/g Processor (intel.com)
All information we can provide are included in this ug.

Thanks,

Ivy