Honored ContributorConnecting an RSA-Coprocessor to a NiosII System
Hi, I designed a rsa coprocessor in Verilog which has to take inputs and put outputs directly into Memory (since arguments are quite large, about 5 or 6 and 1024 bit each). So I made the Coprocessor memory-side connections compatible with the user logic template of the Avalon MM Masters templates and wrote a verilog wrapping module which includes the Coprocessor itself plus two Avalon MM Masters (one for reading and one for writing). Now the wrapper module has two Avalon masters interfaces that I connect to the SDRAM in SOPC Builder (I have to test it on a DE2 Board) and a custom interface (with the programming logic of my own coprocessor) which, by now, I have configured as a Conduit. The problem with this is that I would like to expose these programming inputs to the system as a set of "control/status registers" where to put the data address, the data length, the start and ready signal and so on. I don't know how to do this: turning the counduit interface into a Avalon MM Slave would force me to put into account some timing constraints typical of that kind of interface. I thought about setting this interface as a Custom instruction Slave and using the two dataa and datab ports for address and length arguments and the start done and reset ports for their purpose, but I don't know if this is feasible and whether I should write some extra logic or the arguments passed in the dataa and datab arguments of the custom instruction would be straightly passed to the input wires of my processor.
What would you suggest? Thanks a lot
