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Altera_Forum
Honored Contributor
Honored ContributorConnecting an RSA-Coprocessor to a NiosII System
Hi, I designed a rsa coprocessor in Verilog which has to take inputs and put outputs directly into Memory (since arguments are quite large, about 5 or 6 and 1024 bit each). So I made the Coprocessor ...
Altera_ForumHonored Contributor
Honored ContributorCan't you add an MM slave interface and use that to control the logic?
Since the avalon bus is slave arbited, you can actually stall the slave access until the logic has performed its master accesses to memory.
