Forum Discussion
Honored ContributorConfiguring TSE & Nichestack
I have Quartus&SBT 11.1, and a board with PHY 83848.
I cannot bring up the eth interface with simple socket example. SOPC configuration is good (i hope), but i can't initialize the software: Your Ethernet MAC address is 00:07:ed:ff:d7:52 prepped 1 interface, initializing... [tse_mac_init] Error opening TX SGDMA init error -22 on net[0] mctest init called IP address of : 0.0.0.0 DHCP timed out, going back to default IP address(es) With a (long) debug session, i saw that tse_mac_device[maxnets] global variable is not properly setted. How can i add a phy profile?39 Replies
Altera_ForumSo You supply MII clock to PLL? Which one: TX or RX? Anyway it's a stupid idea... Use DDR controller clock output for the whole system.
- Altera_Forum
No.
My PHY want an external oscillator (25 MHz), i'm suppling it via fpga. I've exported a PLL output clock@25 MHz. Anyway, i've checked with another clock source to the PHY, it still work if my sysclk PLL is set to normal mode, but it stucks when i set it to no compensation. It seems a bug inside Altera's tools. Ah, my external crystal oscillator feed two pll (sysclk and ddr's pll) with the same input pin, it's okay? - Altera_Forum
Why not to use only ddr controller clock outputs? It already takes a PLL, so use that for the whole system. 133MHz is possible, but probably too much. Why not to use half rate clock output for all the components? Then You would need no clock crossing bridge, since the whole system would be synchronous.
- Altera_Forum
Have you already solved this problem? I've just encountered with the same problem with you and I tried all method mentioned in this thread but doesn't work.
I hope you can help me in some degree... - Altera_Forum--- Quote Start --- Have you already solved this problem? I've just encountered with the same problem with you and I tried all method mentioned in this thread but doesn't work. I hope you can help me in some degree... --- Quote End --- Yep, the problem is a bug inside the SOPC buildeir. When i started a fresh new project everything goes ok, but when inside SOPC i modified the clk frequency of DDR the SOPC builder failed to generate appropiate files and then likely some internal timing violation occurs. The problem is 100% replicable with Nios 11.1sp2 with DDR block and TSE. If you have a similar issue, start a new project and rebuild manually from scratch the SOPC configuration. P.S. SOPC builder even when it failed to generate appropiate files still show "generated successfully" at the end, however in the middle of the log i saw a "failed"
- Altera_Forum
Thank a lot. But there are somewhere different between your system and mine. There is no DDR RAM on my board, so i use a on-chip memory(500K) instead. Thus, my developing environment is Nios 11.0 with no service pack.
- Altera_Forum
I have a similar looking system, anything specifically in the system that you'd recommend changing?
- Altera_Forum--- Quote Start --- I have a similar looking system, anything specifically in the system that you'd recommend changing? --- Quote End --- If you have a DDR controller and TSE, simply don't change the DDR clock frequency after the first time. If you have to modify the frequency, start a fresh new SOPC project.
- Altera_Forum--- Quote Start --- If you have a DDR controller and TSE, simply don't change the DDR clock frequency after the first time. If you have to modify the frequency, start a fresh new SOPC project. --- Quote End --- Thanks, I was actually curious about Socrates message about the SOPC system being a mess... not sure if the way the addresses are assigned is not good practice, or if it's something else. My Qsys system looks similar, so just looking for ways to possibly improve it.
