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Altera_Forum
Honored Contributor
Honored ContributorConfiguring TSE & Nichestack
I have Quartus&SBT 11.1, and a board with PHY 83848. I cannot bring up the eth interface with simple socket example. SOPC configuration is good (i hope), but i can't initialize the software: ...
Altera_ForumHonored Contributor
Honored ContributorWhy not to use only ddr controller clock outputs? It already takes a PLL, so use that for the whole system. 133MHz is possible, but probably too much. Why not to use half rate clock output for all the components? Then You would need no clock crossing bridge, since the whole system would be synchronous.
