configuring a new system

So you downloaded the .sof to the target then tried to launch your application through the IDE – is that correct?

Are you sure your hardware is configured correctly? If you are using the dev kit try adding an output that will drive a LED or something that lets you know the processor is running.

Hi all!

Maybe you should detail us how you configured the Reset Addess (inSOPC Builder) and where you put .text and .data. (in Nios II IDE).

Your code could be unreachable...

Bye! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

Hi,

I have been experiencing exactly the same problem as Rakesh, however in my case trying to bring up my own board design.

The error message doesn&#39;t provide me much help of what to do next!

so... To try and track down things, I&#39;ve re-hashed the design to avoid all external i/o and run entirely within the EP1C12 I&#39;m targetting. So I have (just) enough on-chip RAM for the alt_main "hello world" application - and to set the onchip_RAM block as as my system code/data memory - but *still* this message appears......?

Using cable "ByteBlaster II [LPT 1]", device 1, instance 0x00

Pausing target processor: not responding

Resetting and trying again: FAILED

Leaving target processor paused

The design downloads okay from Quartus - but from the NIOS IDE when I run-target-hardware that message is all I get?

Does the reset on NIOS need to be issued for it to work after configuration? I only expected to need to use it as my watchdog reset - At the moment it is tied to VCC on the schematic, since I don&#39;t want to debug my external watchdog circuit right now!

Has anybody any ideas what I could try next?

Thanks!

;O)

Can you describe your resets in more detail (do you have an I/O associated to it, general reset after download, the watchdog is the reset only, etc...)

If you have the watchdog feeding the Nios as the reset, then I would "AND" it with a real reset (assuming your resets are coming in active low).

Hi,

At the moment I do not have any reset signal at all. I just set it to vcc on the schematic.

What exactly is the NIOS IDE trying to do via the Jtag port? Is there some trace available to see why it is unhappy?

Thanks!

Basically the design is dervied from the Nios DevKit reference design - so it will look familiar - http://tinyurl.com/69rnw (http://tinyurl.com/69rnw)

The 50Mhz clock is there, because I have some logic producing a flashing LED?

This is quite a riddle, with not too many clues!!! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif

Hey!, my design is working now? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/ohmy.gif

Since my design started with the dev.kit schematic, only thing I noticed was when I double-clicked the sdram-pll.....

...I noticed that it was setup for Stratix (rather than cyclone) - so I set that to cyclone and re-plugged in the parameters?

Could that have been it? It&#39;s nice to see it working - but I&#39;m worried if this is some borderline flakey-thing?

oh well. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif

Did you start off with a Stratix design? If not, what version and build number do you have for Nios?

*Edit: Also what ref. design were you using (device, vhdl/verilog, and type (standard, full....etc))