Comment block in ModelSim?

Use a condition that is always false

if {0} {
  #  code that never gets executed
}

What HDL? Verilog supports blocks using /* */, or line by line using //. VHDL uses -- for each line. Modelsim may let you select a bunch of text and insert --'s, but it's been awhile since I've used it.

This is for a .do file (not a vhdl or verilog file)

Thanks Dave for your reply however its not quite what I wanted. I wanted to put in several lines of comments for instruction to me for when I open it again months later and have forgotten what I was doing :confused: . Its just a pain to manually add "#" to each line!

if {0} {
  #  code that never gets executed
}

its not really that much of a bother is it?

Yeah I guess. I just thought I was missing something and there was an easy way to do it. I guess not