Hello again, I am trying to increase the data and instruction cache to test if the speed increases when reading data from the UART. At first, I tried making it four times bigger, Quartus said it couldn&#39;t fit into the device, so I eliminated the VGA and Audio modules in SOPC (I am not using them). After that I increased Instruction Cache to 8 KBytes, and Data Cache to 4 KBytes, which is the double of what I had by default. Quartus compiles the project succesfully, and everything is loaded into the FPGA. However, when I open nios2-terminal it never boots correctly, It just freezes after "Uncompressing Linux........ok, booting the kernel" And then nothing happens. I don&#39;t know if I should change something in the kernel or app config. Because I&#39;ve tried so far with different combinations of Data and Instruction Cache sizes, but none of them boots correctly, except for the default values (4K Instruction and 2K data). Does the Operating System register automatically the size of the cache for both instruction and data? I haven&#39;t modified the Cache Line Size, it is still in 4 Bytes. Does it have anything to do with the Quartus License? I don&#39;t think so.. Any configuration trick on Make Menuconfig? I thought this would be a trivial modification but it turns out it isn&#39;t... perhaps I overlooked something but not sure. To be honest, I had never changed the size of these memories. Any ideas on this please? :S Regards, Francisco

Hi, we have changed the size of data and instruction cache many times to optimize speed/fpga size. We have had no boot problems as a result of changing these. Just rebuild the kernel and run. Are you sure you didn&#39;t inadvertently change the reset/exception vector addresses. It sounds to me like something is wrong beyond the cache.

Hello halfdome, Thanks for your fast answer. My configuration is the following on SOPC Builder when editing the Nios II Processor. Reset Vector= Memory: cfi_flash_0 Offset 0x0 Exception Vector= Memory sdram_0 Offset 0x20 Instruction Cache 4 KBytes Data Cache 2 KBytes Data Cache Line Size 4 Bytes Bursts Disabled Tightly Coupled master ports disabled. Like this, it works correctly. And then I only change the size of either Cache Memories. Regenerate the system, Recompile the project. After that: Make vendor_hwselect Make romfs Make and then try to run the OS, and nothing. Perhaps I am missing a step? Your help is greatly appreciated. Regards, Francisco News: I&#39;ve made more tests and apparently it starts to boot. It starts to show all the messages that correspond to the normal boot. However, it stops at some point. It is never the same. Sometimes at the USB messages, others at the Ethernet messages. But it never reaches the console. There is also one message after "Shell invoked to run file /etc/rc" that says Reading Command line: Innapropiate ioctl for device

Did you check whether any peripheral had its base address/IRQ changed in SoPC Builder? if so, did you run make vendor_hwselect again? I don&#39;t know if this would be necessary, but it is one of the first things I&#39;d try. Good luck, Ricardo.

<div class='quotetop'>QUOTE (jasinski @ Jul 14 2009, 07:33 AM) <{post_snapback}> (index.php?act=findpost&pid=23102)</div> --- Quote Start --- Did you check whether any peripheral had its base address/IRQ changed in SoPC Builder? if so, did you run make vendor_hwselect again? I don&#39;t know if this would be necessary, but it is one of the first things I&#39;d try. Good luck, Ricardo.[/b] --- Quote End --- Hello Ricardo, Thank you. Yes, In order to make space for a greater cache (it uses more M4K blocks), I eliminated the VGA module and the Audio Module. Then: - Automatically reassigned the base Addresses in SOPC - Regenerated the system, and took out the corresponding pins in the top level. - Recompiled the project - Run vendor_hwselect Still nothing. I&#39;ll check if there is an extra PLL for the audio or VGA that I missed just to make sure it is not there. Francisco

Ok, I&#39;m totally guessing now, but are you sure removed all references to the VGA and audio modules from the design? Also, if you have not done so already, it may be worthwhile to disable those drivers in the kernel configuration too. Good luck,

Altera_Forum

Honored Contributor

16 years ago

Changing the Size of Data and Instruction Cache

Hello again,

I am trying to increase the data and instruction cache to test if the speed increases when reading data from the UART. At first, I tried making it four times bigger, Quartus said it couldn't fit into the device, so I eliminated the VGA and Audio modules in SOPC (I am not using them). After that I increased Instruction Cache to 8 KBytes, and Data Cache to 4 KBytes, which is the double of what I had by default.

Quartus compiles the project succesfully, and everything is loaded into the FPGA. However, when I open nios2-terminal it never boots correctly, It just freezes after "Uncompressing Linux........ok, booting the kernel" And then nothing happens. I don't know if I should change something in the kernel or app config. Because I've tried so far with different combinations of Data and Instruction Cache sizes, but none of them boots correctly, except for the default values (4K Instruction and 2K data).

Does the Operating System register automatically the size of the cache for both instruction and data? I haven't modified the Cache Line Size, it is still in 4 Bytes.

Does it have anything to do with the Quartus License? I don't think so..

Any configuration trick on Make Menuconfig?

I thought this would be a trivial modification but it turns out it isn't... perhaps I overlooked something but not sure. To be honest, I had never changed the size of these memories.

Any ideas on this please? :S

Regards,

Francisco

12 Replies

Altera_Forum

Honored Contributor

16 years ago

Hello again lads,

So I started the system from scratch. I did "git clean -f -x -d" and lost all changes. First I compiled the quartus project including the larger cache memories (8Inst and 4Data), then started from make menuconfig with default options.

then make vendor_hw select

make romfs

make

nios2-configure sof

nios2-download -g

nois2-terminal

the results, the same :( below is a message of where it stops most frequently.

NiosII EDS]$ nios2-terminal
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster ", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
Uncompressing Linux... Ok, booting the kernel.
Linux version 2.6.30 (pancho@holaamigos) (gcc version 3.4.6)# 5 PREEMPT Tue Jul 14 20:19:15 CDT 2009
uClinux/Nios II
Built 1 zonelists in Zone order, mobility grouping off.  Total pages: 2032
Kernel command line:
NR_IRQS:32
PID hash table entries: 32 (order: 5, 128 bytes)
Dentry cache hash table entries: 1024 (order: 0, 4096 bytes)
Inode-cache hash table entries: 1024 (order: 0, 4096 bytes)
Memory available: 5352k/2556k RAM, 0k/0k ROM (1669k kernel code, 887k data)
Calibrating delay loop... 46.48 BogoMIPS (lpj=232448)
Mount-cache hash table entries: 512
net_namespace: 264 bytes
NET: Registered protocol family 16
init_BSP(): registering device resources
bio: create slab <bio-0> at 0
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 512 (order: 0, 4096 bytes)
TCP bind hash table entries: 512 (order: -1, 2048 bytes)
TCP: Hash tables configured (established 512 bind 512)
TCP reno registered
NET: Registered protocol family 1
io scheduler noop registered
io scheduler deadline registered (default)
ttyJ0 at MMIO 0x19020f0 (irq = 2) is a Altera JTAG UART
console  enabled
ttyS0 at MMIO 0x1902040 (irq = 3) is a Altera UART
dm9000 Ethernet Driver, V1.31

Exactly the same line as before. NOw I've got to build again all the drivers. Good thing I worte them down hehe.

Still haven't been able. Any ideas are welcome.

Thank you all

Francisco

Altera_Forum
Honored Contributor
16 years ago
Hello Friends,

I have managed to run the system with the configuration I sent you. This is with 8K Instruction Cache and 2K Data Cache. This configuration is one step below what I actually need. I am trying to run the system with 16K Instruction Cache and 2K Data Cache. Do you think it is possible? I only modified this parameter in SOPC Builder for the Nios II cpu.

I have already compiled the project with these characteristics and it says everything's fine. However, I am still having the same problem. The OS (uClinux) does not boot correctly.

Is there a relation that must be maintained between the sizes of data and instruction cache?
Is this within the DE2 Board capabilities?

I have a DE2-70 Board which I could use if a bigger device is needed.

Thank you

FRancisco

Forum Discussion

Changing the Size of Data and Instruction Cache

12 Replies

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