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Altera_Forum
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16 years ago

Changing the Size of Data and Instruction Cache

Hello again, I am trying to increase the data and instruction cache to test if the speed increases when reading data from the UART. At first, I tried making it four times bigger, Quartus said ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hello Friends,

I have managed to run the system with the configuration I sent you. This is with 8K Instruction Cache and 2K Data Cache. This configuration is one step below what I actually need. I am trying to run the system with 16K Instruction Cache and 2K Data Cache. Do you think it is possible? I only modified this parameter in SOPC Builder for the Nios II cpu.

I have already compiled the project with these characteristics and it says everything's fine. However, I am still having the same problem. The OS (uClinux) does not boot correctly.

Is there a relation that must be maintained between the sizes of data and instruction cache?

Is this within the DE2 Board capabilities?

I have a DE2-70 Board which I could use if a bigger device is needed.

Thank you

FRancisco