Honored ContributorHi,
Does the CFI flash software driver support 32-bits flash? My QSYS system is having 32-bits ext flash. When I tried memory test from Eclipse template, it always fails to open the flash. It seems like the HAL API couldn't open my 32-bits flash. I've ensured all the pins connections are done. Anyone faced this problem before? Thanks, Carid-
Honored Contributorshould be supported!
cause the address bus connect,must be avalon A2 to flash A0(flash no byte enable)Honored ContributorThanks for the reply.
Did you mean I have to turn on the 'byteenable' signal for my ext_flash? If yes, where should this signal be connected to in my top level? I've ensured both fsm_a[0] and fsm_a[1] are left unconnected as it's 32-bit flash. The signal connection begins with fsm_a[2] and so on. Thank you. Carid-Honored ContributorIf your flash memory only supports 32bit accesses, you should leave byteenable signals unconnected.
addr[2] from the tristate bus should be connected to A0 pin on flash memory, addr[3] to flash A1, and so on. If your flash memory also supports 8 and 16bit modes, you may need to connect tristate addr[n] to flash A[n] because the flash memory itself uses byte addressing. Refer to flash datasheetHonored ContributorAlso, if the 32bit flash is actually made from two 16bit parts you need to take special care during any write/erase operations to ensure that not only are both devices given the requests, but that the driver actually waits for both parts to finish,
(Fixing that bug was the first thing I had to do to some test environment for a strongarm development board.)Honored ContributorThe Stratix-V FPGA devkit board is actually using 16bitx2 CFI.
Quartus Programmer works fine. PFL configuration work fine too. In terms of NIOS tools, such as nios2-flash_programmer, it should have been fixed after Q11.1 and should work.Honored ContributorThanks all.
Yes, my 32-bits flash is made up of 2 16-bits single flash. The data lines are from d[0] - d[15] for 1st flash and d[16] - d[31] for 2nd flash. I've ensured that add[2] is connected to the FIRST address pin on flash memory chip. "you need to take special care during any write/erase operations to ensure that not only are both devices given the requests, but that the driver actually waits for both parts to finish" Is Altera CFI software driver able to do this? Which Stratix V FPGA devkit did you mean? As far as I'm concerned, Altera.com has the latest SV devkit which is 100g development kit, stratix v gx edition (http://www.altera.com/products/devkits/altera/kit-stratix-v-gx-100g.html). This devkit only has 1 CFI flash. Did you mean that as of now, Altera nios tools couldn't support 16bits x 2 CFI? Thanks.Honored ContributorThe s5devkit is not yet on the web. However, you can see the info from here.
Kit Installer: ftp://ftp.altera.com/outgoing/devkit/11.1/stratixvgx_5sgxea7kf40es_fpga_v11.1.2.exe Reference Manual: http://www.altera.com/literature/manual/rm_svgx_fpga_dev_board.pdf User Guide: http://www.altera.com/literature/ug/ug_svgx_fpga_dev_kit.pdfHonored ContributorThanks nekojiru. Looks like the BUP software files have been modified for the 16bits x 2 CFI flash. E.g. instead of writing 0x98, it has now become writing 0x00980098 for the 2x 16-bits CFI flash. Am I right?
Honored ContributorThat is the sort of thing it must do (I can't remember the command values!).
There is also likely to be a loop where it waits for a bit to change - indicating that the write/erase is complete. That code must wait for the bit to change in both the high and low halves of the word - so that both chips have finished.Honored Contributor@nekojiru, do you know which version of ACDS will start supporting the 16bits x2 CFI? There is a IP folder containing the 16bits x2 CFI drivers in the BUP design folder. Perhaps, I will have a look on how it's implemented.
